Memory set with tag setting
These instructions perform a memory set using the value in the bottom byte of the source register and store an Allocation Tag to memory for each Tag Granule written. The Allocation Tag is calculated from the Logical Address Tag in the register which holds the first address that the set is made to. The prologue, main, and epilogue instructions are expected to be run in succession and to appear consecutively in memory: SETGP, then SETGM, and then SETGE.
SETGP performs some preconditioning of the arguments suitable for using the SETGM instruction, and performs an IMPLEMENTATION DEFINED amount of the memory set. SETGM performs an IMPLEMENTATION DEFINED amount of the memory set. SETGE performs the last part of the memory set.
The inclusion of IMPLEMENTATION DEFINED amounts of memory set allows some optimization of the size that can be performed.
The architecture supports two algorithms for the memory set: option A and option B. Which algorithm is used is IMPLEMENTATION DEFINED.
Portable software should not assume that the choice of algorithm is constant.
After execution of SETGP, option A (which results in encoding PSTATE.C = 0):
After execution of SETGP, option B (which results in encoding PSTATE.C = 1):
For SETGM, option A (encoded by PSTATE.C = 0), the format of the arguments is:
For SETGM, option B (encoded by PSTATE.C = 1), the format of the arguments is:
For SETGE, option A (encoded by PSTATE.C = 0), the format of the arguments is:
For SETGE, option B (encoded by PSTATE.C = 1), the format of the arguments is:
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| sz | 0 | 1 | 1 | 1 | 0 | 1 | 1 | 1 | 0 | Rs | x | x | 0 | 0 | 0 | 1 | Rn | Rd | |||||||||||||
| o0 | op1 | op2 | |||||||||||||||||||||||||||||
if !IsFeatureImplemented(FEAT_MOPS) || !IsFeatureImplemented(FEAT_MTE) || sz != '00' then UNDEFINED; SETParams memset; memset.d = UInt(Rd); memset.s = UInt(Rs); memset.n = UInt(Rn); constant bits(2) options = op2<1:0>; constant boolean nontemporal = options<1> == '1'; case op2<3:2> of when '00' memset.stage = MOPSStage_Prologue; when '01' memset.stage = MOPSStage_Main; when '10' memset.stage = MOPSStage_Epilogue; otherwise UNDEFINED;
For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors, and particularly Memory Copy and Memory Set SET*.
CheckMOPSEnabled(); CheckSETConstrainedUnpredictable(memset.n, memset.d, memset.s); constant bits(8) data = X[memset.s, 8]; MOPSBlockSize B; memset.is_setg = TRUE; memset.nzcv = PSTATE.<N,Z,C,V>; memset.toaddress = X[memset.d, 64]; if memset.stage == MOPSStage_Prologue then memset.setsize = UInt(X[memset.n, 64]); else memset.setsize = SInt(X[memset.n, 64]); memset.implements_option_a = SETGOptionA(); constant boolean privileged = (if options<0> == '1' then AArch64.IsUnprivAccessPriv() else PSTATE.EL != EL0); constant AccessDescriptor accdesc = CreateAccDescSTGMOPS(privileged, nontemporal); if memset.stage == MOPSStage_Prologue then if memset.setsize > ArchMaxMOPSSETGSize then memset.setsize = ArchMaxMOPSSETGSize; if ((memset.setsize != 0 && !IsAligned(memset.toaddress, TAG_GRANULE)) || !IsAligned(memset.setsize<63:0>, TAG_GRANULE)) then AArch64.Abort(memset.toaddress, AlignmentFault(accdesc)); if memset.implements_option_a then memset.nzcv = '0000'; memset.toaddress = memset.toaddress + memset.setsize; memset.setsize = 0 - memset.setsize; else memset.nzcv = '0010'; memset.stagesetsize = MemSetStageSize(memset); if memset.stage != MOPSStage_Prologue then CheckMemSetParams(memset, options); if (memset.stagesetsize != 0 || MemStageSetZeroSizeCheck()) then if memset.setsize != 0 && !IsAligned(memset.toaddress, TAG_GRANULE) then AArch64.Abort(memset.toaddress, AlignmentFault(accdesc)); if !IsAligned(memset.setsize<63:0>, TAG_GRANULE) then AArch64.Abort(memset.toaddress, AlignmentFault(accdesc)); integer tagstep; bits(4) tag; bits(64) tagaddr; AddressDescriptor memaddrdesc; PhysMemRetStatus memstatus; integer memory_set; boolean fault = FALSE; if memset.implements_option_a then while memset.stagesetsize < 0 && !fault do // IMP DEF selection of the block size that is worked on. While many // implementations might make this constant, that is not assumed. B = SETSizeChoice(memset, 16); assert B <= -1 * memset.stagesetsize && B<3:0> == '0000'; (memory_set, memaddrdesc, memstatus) = MemSetBytes(memset.toaddress + memset.setsize, data, B, accdesc); if memory_set != B then fault = TRUE; else tagstep = B DIV TAG_GRANULE; tag = AArch64.AllocationTagFromAddress(memset.toaddress + memset.setsize); while tagstep > 0 do tagaddr = memset.toaddress + memset.setsize + (tagstep - 1) * TAG_GRANULE; AArch64.MemTag[tagaddr, accdesc] = tag; tagstep = tagstep - 1; memset.setsize = memset.setsize + B; memset.stagesetsize = memset.stagesetsize + B; else while memset.stagesetsize > 0 && !fault do // IMP DEF selection of the block size that is worked on. While many // implementations might make this constant, that is not assumed. B = SETSizeChoice(memset, 16); assert B <= memset.stagesetsize && B<3:0> == '0000'; (memory_set, memaddrdesc, memstatus) = MemSetBytes(memset.toaddress, data, B, accdesc); if memory_set != B then fault = TRUE; else tagstep = B DIV TAG_GRANULE; tag = AArch64.AllocationTagFromAddress(memset.toaddress); while tagstep > 0 do tagaddr = memset.toaddress + (tagstep - 1) * TAG_GRANULE; AArch64.MemTag[tagaddr, accdesc] = tag; tagstep = tagstep - 1; memset.toaddress = memset.toaddress + B; memset.setsize = memset.setsize - B; memset.stagesetsize = memset.stagesetsize - B; UpdateSetRegisters(memset, fault, memory_set); if fault then if IsFault(memaddrdesc) then AArch64.Abort(memaddrdesc.vaddress, memaddrdesc.fault); else constant boolean iswrite = TRUE; HandleExternalAbort(memstatus, iswrite, memaddrdesc, B, accdesc); if memset.stage == MOPSStage_Prologue then PSTATE.<N,Z,C,V> = memset.nzcv;