SXTH
Sign Extend Halfword extracts a 16-bit value, sign-extends it to
the size of the register, and writes the result to the destination register.
This is an alias of
SBFM.
This means:
-
The encodings in this description are named to match the encodings of
SBFM.
- The description of SBFM gives the operational pseudocode, any constrained unpredictable behavior, and any operational information for this instruction.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| sf | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 0 | N | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | Rn | Rd |
| opc | | | immr | imms | | |
32-bit (sf == 0 && N == 0)
SXTH <Wd>, <Wn>
is equivalent to
SBFM <Wd>, <Wn>, #0, #15
and is always the preferred disassembly.
64-bit (sf == 1 && N == 1)
SXTH <Xd>, <Wn>
is equivalent to
SBFM <Xd>, <Xn>, #0, #15
and is always the preferred disassembly.
Assembler Symbols
| <Wd> |
Is the 32-bit name of the general-purpose destination register, encoded in the "Rd" field.
|
| <Wn> |
Is the 32-bit name of the general-purpose source register, encoded in the "Rn" field.
|
| <Xd> |
Is the 64-bit name of the general-purpose destination register, encoded in the "Rd" field.
|
Operation
The description of SBFM gives the operational pseudocode for this instruction.
Operational information
If PSTATE.DIT is 1:
-
The execution time of this instruction is independent of:
-
The values of the data supplied in any of its registers.
-
The values of the NZCV flags.
-
The response of this instruction to asynchronous exceptions does not vary based on:
-
The values of the data supplied in any of its registers.
-
The values of the NZCV flags.