RISC-V Features (Debugging with GDB)

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#### G.5.12 RISC-V Features

The ‘`org.gnu.gdb.riscv.cpu`’ feature is required for RISC-V targets. It should contain the registers ‘`x0`’ through ‘`x31`’, and ‘`pc`’. Either the architectural names (‘`x0`’, ‘`x1`’, etc) can be used, or the ABI names (‘`zero`’, ‘`ra`’, etc).

The ‘`org.gnu.gdb.riscv.fpu`’ feature is optional. If present, it should contain registers ‘`f0`’ through ‘`f31`’, ‘`fflags`’, ‘`frm`’, and ‘`fcsr`’. As with the cpu feature, either the architectural register names, or the ABI names can be used.

The ‘`org.gnu.gdb.riscv.virtual`’ feature is optional. If present, it should contain registers that are not backed by real registers on the target, but are instead virtual, where the register value is derived from other target state. In many ways these are like GDBs pseudo-registers, except implemented by the target. Currently the only register expected in this set is the one byte ‘`priv`’ register that contains the target’s privilege level in the least significant two bits.

The ‘`org.gnu.gdb.riscv.csr`’ feature is optional. If present, it should contain all of the target’s standard CSRs. Standard CSRs are those defined in the RISC-V specification documents. There is some overlap between this feature and the fpu feature; the ‘`fflags`’, ‘`frm`’, and ‘`fcsr`’ registers could be in either feature. The expectation is that these registers will be in the fpu feature if the target has floating point hardware, but can be moved into the csr feature if the target has the floating point control registers, but no other floating point hardware.

The ‘`org.gnu.gdb.riscv.vector`’ feature is optional. If present, it should contain registers ‘`v0`’ through ‘`v31`’, all of which must be the same size.

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